Senior ASIC Digital Design Engineer

Basic Qualifications

Education Requirements:

Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.  

Clearance Requirements:

Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

Knowledge, Skills and Abilities:

What You’ll Get to Do:

• Lead a team of digital design engineers to create a security system on a chip.
• Collaborate with team members and across teams to explore and clearly identify real problems and solutions.
• Develop and define the microarchitecture of new IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions.
• Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages.
• Integrate complex systems that instantiate both the organization's and third party IP.
• Contribute to all aspects of design success from specification to production.
• Apply our state-of-the-art IP to ASIC and FPGA products in the real world.
• Define and improve high-quality design methods and processes.
• Mentor and guide other ASIC design engineers.
• Identifies opportunities to apply AI for continuous improvement and innovation.

Knowledge, Skills and Abilities:

• Solid technical background with at least 5 years of experience in FPGA or ASIC product development
• Team leadership experience.
• Ability to communicate clearly in person and in written documentation
• Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
• In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
• Strong analytical and problem solving skills
• Extreme attention to detail
• A willingness to roll up one’s sleeves to get the job done
• Skilled at working effectively with cross functional teams

#LI-Hybrid

Target salary range: USD $142,166.00/Yr. - USD $150,000.00/Yr. This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans